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Advances, Systems and Applications

Table 2 VBSME accelerator area and performance results with a custom RTL-designed memory subsystem

From: IO and data management for infrastructure as a service FPGA accelerators

# of PPUs

Areaa

   

Performance

 
 

LUTs

DFFs

Target resolution

Freq

fps

 

#(K)

%

#(K)

%

 

(MHz)

 

1

8.71

4.20

3.42

1.65

640 ×480 (VGA)

200.6

28

2

18.5

8.92

5.49

2.65

800 ×608 (SVGA)

199.0

34

4

37.8

18.2

9.64

4.65

1024 ×768 (XVGA)

198.3

42

8

76.4

36.8

18.0

8.68

1920 ×1088 (HD Video)

198.3

31

16

154

74.3

34.6

16.7

1920 ×1088 (HD Video)

198.3

62

  1. aXilinx’s Virtex 5 devices use 4 DFFs & 4 6-input LUTs per Slice