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Advances, Systems and Applications

Table 3 VBSME accelerator area and performance results with MicroBlaze (125 MHz) based data delivery

From: IO and data management for infrastructure as a service FPGA accelerators

# of PPUs

Area

     

Performance

 
 

LUTs

DFFs

LUTs % Increase

DFFs % Increase

Freq (MHz)

fps

 

#(K)

%

#(K)

%

    

1

22.7

10.9

6.70

9.11

6.70

7.46

100

15

2

32.5

15.7

6.78

10.1

6.78

7.45

100

16

4

51.8

25.0

6.80

12.1

6.80

7.45

100

20

8

90.4

43.6

6.80

16.1

6.80

7.42

100

15

16

168

81.0

6.70

24.2

6.70

7.50

100

30

  1. *Xilinx’s Virtex 5 devices use 4 DFFs & 4 6-input LUTs per Slice