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Advances, Systems and Applications

Table 4 DIALIGN alignment accelerator with custom HW interfaces vs. HW/SW IO interfaces

From: IO and data management for infrastructure as a service FPGA accelerators

 

Areaa

 
 

LUTs

DFFs

LUTs % Increase

DFFs % Increase

Accelerator frequency (MHz)

MicroBlaze frequency (MHz)

 

#(K)

%

#(K)

%

    

HW interface

51.0

73.8

36.9

53.4

  

67.7

N/A

HW/SW interface with Microblaze

64.5

93.3

52.0

75.2

19.5

21.8

67.7

125

  1. aXilinx’s Virtex 5 devices use 4 DFFs & 4 6-input LUTs per Slice